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mt8870 details and pins diagram
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Ψ DTMF DECODER (MT8870) :

 

PIN DIAGRAM:

               

BLOCK DIAGRAM:

 

 

 

Features

• Complete DTMF Receiver

• Low power consumption

• Internal gain setting amplifier

• Adjustable guard time

• Central office quality

• Power-down mode

• Inhibit mode

• Backward compatible with MT8870C/MT8870C-1

 

Applications

• Receiver system for British Telecom (BT) or CEPT Spec (MT8870D-1)

• Paging systems

• Repeater systems/mobile radio

• Credit card systems

• Remote control

• Personal computers

• Telephone answering machine

 

 

Description

The MT8870D/MT8870D-1 is a complete DTMF receiver integrating both the band -split filter and digital decoder functions. The filter section uses switched capacitor techniques for high and low group filters; the decoder uses digital counting techniques to detect and decode all 16 DTMF tone-pairs into a 4-bit code. External component count is minimized by on chip provision of a differential input amplifier, clock oscillator and latched three-state bus interface.

 

Pin Description

 

1.  IN+      Non-Inverting Op-Amp (Input).

2.  IN-       Inverting Op-Amp (Input).

 

3.  GS      Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor.

 

4.  V-Ref   Reference Voltage (Output). Nominally VDD/2 is used to bias inputs at          mid-rail .

 

5.  INH      Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C and D. This pin input is internally pulled down.

 

6.  PWDN  Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This pin input is internally pulled down.

 

7.  OSC1   Clock (Input).

 

8.  OSC2   Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2 completes the internal oscillator circuit.

 

9.  VSS    Ground (Input). 0 V typical.

 

10.  TOE  Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is pulled up internally.

 

11-14.  Q1-Q4 Three State Data (Output). When enabled by TOE, provide the code corresponding to the last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high impedance.

 

15.  StD  Delayed Steering (Output).Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below VTSt.

 

 

 

16.  ESt  Early Steering (Output). Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.

 

17.  St/GT  Steering Input/Guard time (Output) Bidirectional. A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St.

 

18.  VDD  Positive power supply (Input). +5 V typical.