Special Function Registers of At89C51
A map of the on-chip memory area called the Special Function Register (SFR) space.
Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in general return random data, and
Write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in future
Products to invoke new features. In that case, the reset or inactive values of the new bits will
Always are 0.
Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 5-
2) And T2MOD (shown in Table 10-2) for Timer 2. The register pair (RCAP2H, RCAP2L) are the
Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.
Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can
Be set for each of the six interrupt sources in the IP register.Memory Organization for At89c51
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K
bytes each of external Program and Data Memory can be addressed.
If the EA pin is connected to GND, all program fetches are directed to external memory.
On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through
1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.
The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel
address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access the SFR space.
For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data
Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.
Programmable Clock Out
A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 12-1. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz (for a 16-MHz operating frequency). To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer. The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation.
Clock-Out Frequency= Oscillator Frequency/( 4 x [65536-(RCAP2H,RCAP2L)])
In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate gen-erator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L.