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What is MAC Architecture**

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MAC is the composition of adders, multipliers and accumulators. Multiplier and adder delays play an important role for the design of MAC. For the enrichment of the speed operation Sklansky adders is used. One implementation of the multiplier could be as a parallel array multiplier. The inputs of the MAC are fetched from the memory location and fed to the multiplier block of the MAC, which will perform the multiplication and give the results to the adder. The function of the adder block is performing the accumulation of the results, and then the results are stored in the memory locations. The function of the conventional MAC unit is given by the following equation

Fig. 1 indicates the functional block diagram of the MAC. Fig. 2 indicating the architecture of the MAC diagram which has been designed in this paper. The design consists of one 4 bit parallel adder based Wallace tree multiplier , one 10 bit accumulator register, one control logic/DeMUX block, one 8 bit register. The two 4 bit numbers are multiplied and stored in 8bit registers. In first clock pulse the numbers are multiplied and the result is added with zero.

Demux are used to determine whether the
generation of convolution sum operation is over. If ctrl signal of demux ‘0’
then the operation is over else eight bit results are again fed to the
accumulator registers. The two new numbers are multiplied in the second clock
pulse and the product is added with first eight bit results. The process is
repeated for four times until the multiplication over. The ctrl signal
generation circuit has been shown in Fig.3. This circuit counts the number of
clock pulses. The mentioned circuit is a down counter which is set at 4_{10}.
For each clock pulse the down counter is decremented by one. When the forth
clock pulse is reached the ctrl signal is ‘0’ and it remains ‘0’ until a new
operation is executed and sets the MAC output results.

Table 1: Power delay analysis of MAC

Parameters |
Pre layout Simulation |
Post Layout Simulation |
Conventional MAC |

Delay(ns) |
0.437 |
0.457 |
0.512 |

Average power(µw) |
2.51 |
2.83 |
3.03 |

Lkg. Power (µw) |
3.8 |
4.1 |
4.23 |

EDP(10 |
0.4793 |
0.591 |
0.794 |

Fig.10. layout of 4 point MAC