Serial to Parallel Converter (S to P):
The functionality of the circuit can be achieved by clock triggered Serial in Parallel out shift registers and de-multiplexers. The selection inputs to the de-multiplexers are fed from an auto generated counter which is driven by a clock signal input. In this paper to avoid the sequential mechanism a fully combinational scheme for serial to parallel conversion has been adopted. The
RTL representation of the combinational serial to parallel converter is shown in Fig. 11. This circuit is providing parallel output as well as serial output depending upon the selection input (Parallel).If ‘Parallel’ input is high then parallel outputs will be taken from the pins y0 to y3 which is indicated in Fig. 11. The clock driven shift registers has been replaced by parallel multiplexer shifters. The elements (bits) needed to be shifted are fed to the multiplexers parallel in the fashion shown in Fig. 11. The select inputs to the multiplexers are fed from a parallel adder which is acting as a combinational counter. The clock input is replaced by a trigger input which is fed to the ‘carry in’ pin of the parallel adder. Again if any zero or one padding is needed then the bit input is fed to the Data in pin at the input side. At the output side the serial and parallel operation is monitored by AND gate arrays which is activated or deactivated depending upon the ‘Parallel’ input. This particular circuit is devised to execute right shift operation. That is why the serial output is taken from the LSB (b0) bit. For left shifting the orientation of the inputs to the multiplexers will be reverse and the serial output will be taken from the MSB (b3) bit.