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parallel to serial converter
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Parallel to Serial Converter (P to S)

 

Parallel to Serial converter has the just reverse mechanism that of Serial to Parallel converter. The functionality of the circuit can be achieved by clock driven Parallel in Serial out shift registers and multiplexers. In this paper the clock triggered shift registers has been replaced by multiplexers connected in parallel and the selection inputs are monitored by a parallel adder which is acting as a combinational counter to avoid the clock triggering and clock skewing. The RTL representation of the combinational parallel to serial converter is shown in Fig. 11. The parallel or serial mechanism is obtained by a selection input (Serial). If the ‘Serial’ input is low the serial data will be taken at the serial data out pin. The particular architecture is devised to achieve parallel outputs as well as serial output depending upon the selection input ‘Serial’. The parallel inputs are fed to the AND gate array which is activated or deactivated by the ‘Serial’ input. The multiplexer inputs are connected in shifted fashion shown in Fig. 11. This orientation is maintained to execute the right shift operation. The same reason forces us to take the serial output from LSB (y0) of the parallel output. For the left shift operation the orientation of the input bit array will be reverse. Similarly the serial output will be taken from the MSB (y3) of the parallel output bit array in case of left shift operation. If any zero or one padding is needed the corresponding input is fed to the ‘Data in’ pin.

 

Table 2: Power delay analysis of Circular Convolution

Parameters

Pre layout Simulation

Post Layout Simulation

Conventional MAC

Delay(ns)

0.754

0.836

0.897

Average power(µw)

3.72

4.341

4.986

Lkg. Power (µw)

4.93

5.142

5.354

EDP(10-24)J-s

2.1148

3.0339

4.011