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hardware implementation of c z transform processor
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Hardware Implementation of C- Z Transform Processor:

 

Let length of the input sequence is N=5.From the fig. 3.

 

             (4.23)

                                                                     

This is a equation of DFT and   is result for the first DFT which is shown in the block diagram.

In this equation a convolution matrix as shown in eq(4.24).

Here the circular convolution matrix is

 

                                       (4.24)                                                                                        

From equation (10) we can define  ,which is result of circular convolution between  as:

 

                 (4.25)      

                                                 

 

                                   (4.26)

                                                                 

Here the 4 points circular convolution matrix is

                                                                  (4.27)

 

Equation (4.24), (4.25), (4.27) are the convolution matrix. This convolution hardware architecture (sec.2) is designed by MAC architecture. This MAC architecture is described under a subsection of circular convolution. And equation (4.23),(4.26) are the DFT equation this DFT architecture is done by CC. So the total delay is less. This DFT process is designed in section (3).