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hardware architecture of egyptian multiplier
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Hardware Architecture of Egyptian Multiplier:

Firstly we take two inputs X, Y to be multiplied. The input X is given to the PISO register. The initial value of clock is set by 0. When the clock signal becomes”0” the output of the register is the shifted value of the input. When the clock of the decrementer circuit is 0 then the initial input of the decrementer which is set by “0100” is continuously decremented until the output of the decrementer is “0000”. Now the input Y is given to the 8 bit shifter controlled by selection line d0, d1 and d2, d3 are don’t care. There is also a 8bit Bit checker unit when the output  of the register is “1” then the input Y is added to the previous shifted value of Y in the 8 bit full adder.

Performance comparison graph of this curcuit is shown in the fig. 6

 

 Fig.  5.  Circuit diagram of 4×4 multiplier

 

 

 

 

 

 

 

 

Fig. 6. Performance comparison graph of 4×4 Egyptian multiplier