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hardware architecture of chirp z transform
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Hardware Architecture of Chirp Z-Transform

  Hardware architecture of CZT:

                                                                                     (4.1)

                                                                       

We put , k=0,1,2……………M-1. Equation (4.1) can be rewritten as,

                                                                (4.2)                                                                

Now for chirp z-transform, consider , k=0,1,2……………M-1   (4.3)

                                   

Putting equation (4.3) in equation (4.1), we get

, k=0,1,2,3,……………..,N-1                                  (4.4)

 

Now 'nk’ can be represented as,                                             (4.5)                                                           

 

using equation (4.5) we can define  as,

                                                (4.6)                                                    

 

Where k=0,1,2,………….M-1. For simplicity if we consider A=1, then equation (4.6) can be written as,

                                          (4.7)

                                                           

Since, ,  and A=1, then it can be asserted that . Now we know that . So W can be expressed as,

                                                                     (4.8)

                                                           

So,  which is the symmetric property.

Now by using De-Moivre’s Theorem, we get,

                              (4.9)                                                   

 

                    (4.10)                          

 

, putting k=0                           (4.11)

                                   

          (4.12)