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Generation of the Convolution Matrix:


As defined in equation the cyclic convolution between two 4-point sequences x and h can be expressed in matrix form as:




It is to be noted that on the right hand side of equation (18), each row of the 44 square matrix can be generated by serial rotation of the input vector X = [X0, X1, X2, X3] from left to right. A 4-bit right shift register {SS_4SS_1SS_2SS_3} has been employed for this purpose with a feedback connection from SS_3 output to SS_4 input via two block of serial to parallel converter and parallel to serial converter as shown in Fig. 11. Initially the line MUX Enable is set low in order to load the input vector X to the registers. After the input sequence is loaded into the registers, MUX Enable is set high to perform the serial rotation on the arrival of each subsequent negative clock edge. The bus line MUX Enable is again set low after the generation of the fourth row of the square matrix before the arrival of the fourth clock edge.




The architecture shown in Fig. 11 has been dedicated for the generation of the elements of the column matrix [z]. This hardware module imposes a serious restriction on the time period of the system clock. The time period of the system clock f should be large enough to allow the evaluation of each Yis to be done within a single clock period. After generating the convolving matrix the convolving matrix is multiplied by the input sequences, and promoted to the input of the MAC. The timing diagram of the MAC inputs is shown in Table 3.