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cyclic convolution formulation form mathematical expressions of dft
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Cyclic Convolution formulation form Mathematical Expressions of DFT:

For prime length DFT we can formulate equation (1) as

Y(0)=

And

Where

And “” denotes the “” operation. T(k) is the cyclic convolution of the sequence {x(i),i=1,2,…….N-1} and the kernels { where  I and k=1,2,…N-1}. Considering a 5 point DFT as an example. The input sequence is given as {x(n), n=0,1,2,3,4} and kernel is (w=),then the equation (3.1) can be expressed as:

                                                    (3.3)                                                   

Alternatively equation (20) can be written as:

                                                                       (3.4)                                         

And

                               (3.5)

The equation shown above is representing the 4 point circular convolution.

 

SIMULATION RESULT ANALYSIS DFT hardware architecture:

All the algorithm of this paper has been designed and their functionality have been checked. Performance analysis of all the algorithms has been calculated on spice simulator by using standard 90nm CMOS technology. Dynamic leakage power, propagation delay, and energy delay product analysis of the 16 point DFT chip is given in Table 1. Input data’s are taken as a regular fashion for experimental purpose.

 

Table 3: Performance analysis of DFT chip for comparison

Architecture used

Delay (ns)

Power (mw)

EDP (10-18 J-s)

Guo

41.3

22.3

38.036

Benhamid

39.6

21.3

3.401

Proposed

37.1

18.7

25.738

 

 

  CONCLUSIONS for DFT hardware architecture:

 

 In this paper, a hardware efficient method for DFT algorithm implementation has been proposed using circular convolution techniques. The proposed architecture uses the advantages of canonical sign digits for addition and multiplication purpose. The implementation result on Spice spectre is presented in this paper and compared to other methods. The proposed DFT chip shows 10%, and 6% improvement in the propagation delay, and 16% and 12% improvement in power consumption as compared to Guo[8] and Benhamid[13] architecture respectively.