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High Speed ASIC Implementation of Chirp Z-Transformation using high speed Discrete Fourier Transformation Techniques






ASIC implementation of high speed Chirp Z-Transformation (CZT) processor using Circular Convolution (CC) technique has been reported in this project. The design methodology was based on the computation of the transformation equation into a circular formulation, which encounter the high speed implementation methodology. The IEEE 754 single precision was considered for twiddle factor representation. The multiplication of the coefficients with twiddle factors have been computed with the help of high speed Multiply and Accumulate (MAC) architecture.  The algorithmic architecture was designed and the performance parameters such as propagation delay, power consumption and hardware utilization was calculated through Xilinx-8.2i simulator. The implementation methodology ensure substantial amount of hardware saving as compared to traditional CORDIC based implementation. Almost 50% speed improvement has been achieved from earlier reported design, e.g. CORDIC based implementation.