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timing report
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TIMING REPORT

 

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

      GENERATED AFTER PLACE-and-ROUTE.

 

Clock Information:

------------------

No clock signals found in this design

 

Asynchronous Control Signals Information:

----------------------------------------

No asynchronous control signals found in this design

 

Timing Summary:

---------------

Speed Grade: -4

 

   Minimum period: No path found

   Minimum input arrival time before clock: No path found

   Maximum output required time after clock: No path found

   Maximum combinational path delay: 18.299ns

 

Timing Detail:

--------------

All values displayed in nanoseconds (ns)

 

=========================================================================

Timing constraint: Default path analysis

  Total number of paths / destination ports: 140 / 8

-------------------------------------------------------------------------

Delay:               18.299ns (Levels of Logic = 9)

  Source:            b<1> (PAD)

  Destination:       diff<7> (PAD)

 

  Data Path: b<1> to diff<7>

                                Gate     Net

    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)

    ----------------------------------------  ------------

     IBUF:I->O             5   0.821   1.260  b_1_IBUF (b_1_IBUF)

     LUT2:I0->O            1   0.551   0.996  A8/A[2].A1/carry85_SW0 (N113)

     LUT4:I1->O            2   0.551   1.216  A8/A[2].A1/carry85 (A8/c<3>)

     LUT4:I0->O            2   0.551   0.945  A8/A[3].A1/carry1 (A8/c<4>)

     LUT3:I2->O            2   0.551   0.945  subtractor_011_xo<1>11 (N3)

     LUT3:I2->O            2   0.551   0.945  A8/A[5].A1/carry1 (A8/c<6>)

     LUT4:I2->O            1   0.551   0.869  subtractor_09_xo<2>2_SW0 (N115)

     LUT3:I2->O            1   0.551   0.801  subtractor_09_xo<2>2 (diff_7_OBUF)

     OBUF:I->O                 5.644          diff_7_OBUF (diff<7>)

    ----------------------------------------

    Total                     18.299ns (10.322ns logic, 7.977ns route)

                                       (56.4% logic, 43.6% route)

 

=========================================================================

CPU : 6.53 / 6.88 s | Elapsed : 7.00 / 7.00 s

 

 

CONCLUSION

 

So we have discussed about the 8 bit architecture of subtraction. Here we have made a graph that denotes the availavility and utilization. Also we hane made a comparison between the architectures that denoted that the proposed algorithm that we have implemented has given a far better result in terms of power and delay.