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sequential alus
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Sequential ALUs                                                                                                           

 

            Although, as we have seen, both multiplication and division can be implemented by combinational logic, it is generally impractical to merge these operations with addition and subtraction into a single, combinational ALU. The reason is two-fold. Combinational multipliers dividers are costly in terms of hardware. They are also much slower than addition and subtraction circuits, a consequence of their many logic levels. An n-bit combinational multiplier or divider is typically composed of n or more levels of add-subtract logic, making multiplication and division at least n times slower than addition or subtraction. The number of gates in the multiply-divide logic is also greater by a factor of about n. Hence except when n is very small, complete ALUs are usually constructed from  low cost sequential  circuits where add and subtract each take one clock cycle, while multiplication and division are multicycle operations.                                                                                                                                          

Basic design. Figure shows a widely used sequential ALU design that aims at minimizing hardware costs. This ALU organization is found in the IAS computer Figure 1.11) and in many computers built after IAS. It is intended to

 

 

Figure 1.4

A 16-bit combinational ALU composed of four 74181s linked by ripple-carry propagation.

           

Figure 1.5                                                                                                                                                               

Structure of a basic sequential ALU.              

                                                                               

 

implement multiplication and division using one of the sequential digit-by-digit shift-and-add/subtract algorithms discussed earlier. Three one-word registers are used for  operand storage: the accumulator AC, the multiplier-quotient register MQ, and the data register DR. AC and MQ are organized as a single register AC.MQ capable of left- and right-shifting. Additional data processing is provided by a combinational ALU capable of addition, subtraction, and logical operations; we will refer to this unit as the add-subtract unit. This unit derives its inputs from AC and DR and places its results in AC. The MQ register is so called because it stores the multiplier during multiplication and the quotient during division. DR stores the multiplicand or divisor, while the result ( product or quotient and remainder ) is stored in the register-pair AC.MQ. The role of these registers is defined concisely as follows:                                                                                        

                        Addition                                 AC :=  AC +  DR                                                        Subtraction                              AC := AC  -  DR                                

                        Multiplication                          AC.MQ :=  DR  X  MQ                                             Division                                   AC.MQ :=  MQ/DR                          

                        AND                                       AC :=  AC and DR                            

                        OR                                          AC :=  AC  or   DR                            

                        EXCLUSIVE- OR                 AC :=  AC  xor  DR                           

                        NOT                                        AC :=  not(AC)                                              

DR can serve as a memory data register to store data addressed by an instruction address field ADR. Then DR can be replaced by M(ADR) in the above list of ALU operations, resulting in a one-address memory-referencing format.