Here we are going to discuss about the subtractor implementation using Vedic mathematics. Vedic Mathematics is the name given to the ancient system of Mathematics which was rediscovered from the Vedas between 1911 and 1918 by Sri Bharati Krsna. Vedic Maths is considered to be the technology and science of order and precision, which maintains the uprightness of unity and also spreads variety with it. It is also said to be the Natural Law’s structuring dynamic; it instinctively designs the source and goal of natural law, which is the orderly theme of evolution.
Here we have used the proposed architecture for the implementation of subtractor. As we know that the various circuits used to execute data processing instructions are usually combined in a single circuit called an arithmetic-logic unit or ALU. The complexity of an ALU is determined by the way in which its arithmetic instructions are realized. So we have very much careful about the architecture that we are using.
Before going to the main portion we have to make a clear idea about the previous works that have been done in the past that leads to the “NIKHILAM SUTRA”.
Most of the known adder architectures can be represented as a parallel prefix adder structure which of consisting of three parts: pre processing, carry ahead network, post processing.
Assuming two binary input vectors A and B, the preprocessing part extracts two signals propagate (p) and generate (g) using two simple logic circuit. The calculation of sum is assigned to the post processing step which is likely pre processing step a time constant operation. This only leaves carry propagation or carry ahead network problem, which is a recursive function, to be addressed. The carry propagation problem can be expressed in terms of prefix problem where for a set of binary inputs that is (xi: i=0,1,2..n) the outputs (yi: i=0,1,..n) are defined by the help of associative binary operator as:
Since the (.) operator is associative it can be grouped into any order and it can be computed in any number of levels. To express the subproduct let us introduce the notation Y, where k is the level of sub product and i:j represents the continuous range that the sub product covers. For the carry propagation let it introduce the sub product couple as (G,P),such that:
(G,P) i:i0=(gi,pi) (3.4)
(G,P) i: jk=(G,P).(G,P) (3.5)
where the desired carryi=Gi:0
Regardless the number of levels necessary to cover the range i:0.Depending on the algorithm the carry propagation structure has different shape. For this the following observations can be made.
The maximum level required to calculate the final carry signal is referred as the depth of the prefix graph and equals to the number of logic levels in the network. The depth of the carry propagate network is a function of bit-width of the input. This number relates roughly to the delay of the network. The total number of binary associative operations within the network determines the active area required to compute the result. Secondary effects like the number of times a sub range is used in subsequent condition.
Some of the previous known adder architectures are discussed in below.