and PG level projects,mini projects and many more here ...





Design of IC 74181 (4-bit ALU)


The main internal features of the 74181 appear in Figure(1.3).The key arithmetic operation of twos-complement addition is implemented by the carry-lookahead method. The adder consists of propagate-generate logic feeding a lookahead circuit that computes carries, and a set of XOR gates that compute the final sum. The 74181s carry-lookahead generator is the same as that given earlier with the addition of propagate and generate outputs (denoted p and g) for extension purposes. However, the pg and sum circuits are also designed to be shared with the logic unit in an efficient, but nonobvious fashion. The modules labeled M1 and M2 generate a pair of 4-bit signals IP and IG that serve as internal propagate and generate, respectively, in the arithmetic mode as minterm sources in the logic mode. From Figure (1.3) we see that each data output function F1 is defined by


                                    Fi = IP XOR  IGi  XOR  ( ICi-1 + M )                                (1.5)            Figure 1.3

A register-level view of the 74181 4-bit ALU                                                                                                                        

for 3> i > 0, where IC denotes the set of four internal carries produced by the carry-lookahead generator. The IP and IG functions are defined by                                                   

                                    IPi  = Ai + BiS0 + BiSi                                                           (1.6)                                                       IGi = AiBi’S 2 + AiBiS3                                                                    (1.7)                                                                                    

In the logic mode of operation, M = 1, so (1.5) becomes                                          


                                    Fi = IPi   XOR  (IGi)’                                                                       (1.8)

                                                                                                                                                                          On substituting (1.6), (1.7) into (1.8) and simplifying, we obtain

                                    Fi = Ai’BiS0’ + Ai’Bi’Si’ + AiB’S2 + AiBiS3                           (1.9)                                                                                                                                          

This expresses Fi(Ai,Bi) in sum of minterms form, with a distinct ( possibly complemented ) select variable controlling each minterm. It therefore produces a different logic function for each of the 16 possible combinations of the S variables, and so is essentially the same as (1.4).Hence with M=1, the 74181 acts as a universal function generator capable of producing any two variable Boolean function F(A,B).            In the arithmetic mode M = O and (1.5) changes to                           


                                    Fi = IPi  XOR  IGi  XOR  ICi-1                                          (1.10)    


This has the general form of a sum (or difference) output. We can interpret the entire output function F= F3F2F1F0 more easily using the arithmetic expression


F = (IP)’ plus (IG)’ plus cin                                                                     (1.11)


which is implied by  when M= 1. Here plus denotes twos-complement addition to distinguish it from + denoting logical OR. When S= 1001, Equations (1.6) imply that IPi and IGi become the usual propagate and generate functions, IPi = Ai + Bi and IGi = AiBi, respectively. Hence the control settings M = 1 and S= 1001 make the 74181 behave like a carry- lookahead adder that computes                                                                                                                         

                                    F = A plus B plus cin                                                            (1.12)


changing S to 0110 produces the twos-complement subtraction                                           

                                    F = A minus B minus cin                                                    (1.13)                  

and effectively reconfigures the ALU.                                  


            The various combinations of S produce a total of 16 different functions in the arithmetic mode, only a few of which are useful. For example, with S = 0100, Equation (1.11) becomes                 

                                    F = 1111 plus 0000 plus cin                                                 (1.14)                  

which is 1111 when  cin = 0, that is, the constant minus-one in twos-complement code. When cin = 1, F changes to 0000, since we are adding plus-one to minus-one. The ability to generate constants like ± 1 and 0 in this way is useful for implementing some types of instructions. 

The 74181s p, g and cout outputs are intended to allow k copies of the 74181 to be combined either using ripple-carry propagation or carry-lookahead to form a 4k-bit ALU. Figure 1.4 shows a 16-bit ALU composed of four 74181 stages, with ripple-carry propagation between stages; compare figure 1.3. Note how the S and M control lines are shared, while the data lines are separate. Note too that no interstage connections are needed for the logic operations because of their bitwise, word-oriented nature. Another interesting feature of the 74181 is its ability to act as a magnitude comparator in conjunction with the carry output c out. The electronic circuits driving the 74181s ( A=B ) output are designed so that when several ( A=B ) lines are wired together as in Figure 1.4, the wired connection outputs the AND function of all its input signals. In other words, the overall ( A=B ) output signal is 1 if and only if each 74181 slice produces ( A=B ) = 1. This type of technology-specific connection is called a wired AND. No extra gates or other “ glue” logic are needed for ripple-carry expansion of the 74181.