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final simulation results in xilinx
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Final simulation results in Xilinx

 

 

 

=========================================================================

*                            Final Report                               *

=========================================================================

Final Results

RTL Top Level Output File Name     : subtractor.ngr

Top Level Output File Name         : subtractor

Output Format                      : NGC

Optimization Goal                  : Speed

Keep Hierarchy                     : NO

 

Design Statistics

# IOs                              : 25

 

Cell Usage :

# BELS                             : 21

#      GND                         : 1

#      LUT2                        : 2

#      LUT3                        : 8

#      LUT4                        : 10

# IO Buffers                       : 25

#      IBUF                        : 16

#      OBUF                        : 9

=========================================================================

 

Device utilization summary:

---------------------------

 

Selected Device : 3s50pq208-4

 

 Number of Slices:                      12  out of    768     1% 

 Number of 4 input LUTs:                20  out of   1536     1% 

 Number of IOs:                         25

 Number of bonded IOBs:                 25  out of    124    20% 

 

 

=========================================================================