The various circuits used to execute data processing instructions are usually combined in a single circuit called an arithmetic-logic unit or ALU. The complexity of an ALU is determined by the way in which its arithmetic instructions are realized. Simple ALUs that performs fixed point addition and subtraction, as well as word based logical operations, can be realized by combinational circuits. ALUs that also perform multiplication and division can be constructed around the circuits developed for these operations in the preceding section. Much more extensive data processing and control logic is necessary to implement floating-point arithmetic in hardware. Some processors having fixed-point ALUs employ special-purpose auxiliary units called arithmetic (co)processors to perform floating-point and other complex numerical functions.
The simplest ALUs combine the functions of twos-complement adder-subtracter with those of a circuit that generates word-based logic functions of the form f(X,Y), for example, AND, XOR, & NOT. They can thus implement most of a CPU’s fixed-point data-processing instructions. Figure 1.1 outlines an ALU that has separate subunits for logical and arithmetic operations. The particular case of operation (logical and arithmetic) to be performed is determined by a “mode” control line M attached to a two-way multiplexer that channels the required result to the output bus Z.
A basic n-bit arithmetic-logic unit (ALU).
The specific operation performed by the desired subunit is determined by a select line S as shown. The ALU’s logical operations are performed bitwise; that is, the same f is applied to every pair of data lines xiyi. The maximum number of distinct logical operations of the form f (xi,yi) is 16, which is the number of distinct truth tables of two Boolean variables. Hence the select bus S needs to be of size 4 at most, as in Fig. 1.1. S can also be used to select up to 16 different arithmetic operations such as X + Y, X – Y, Y – X, X + 1 (increment), X – 1 (decrement), and so on, as needed.
The logical operations in figure can be obtained by generating all four minterms of f(xi,yi), namely,
m3= xiyi m2= xiyi’ m1= xi’yi mo= xi’yi’ (1.1)
for every pair xi,yi of data bits and by using the control lines S=S3S2S1S0 to select desired subsets of the minterms to be ORed together. In particular, if we construct the sum-of-products expression
f(xi,yi) = m3S3 + m2S2 + m1S1 + m0S0 (1.2)
= xiyiS3 + xiyi’S2 + xi’yiS1 + xi’yi’S0 (1.3)
then we see that every combination of S3S2S1S0 produces a different function. For example, S = 0110 makes f(xi,yi) = xiyi’ + xi’yi, which is EXCLUSIVE-OR. Because of the bitwise nature of the logical operations, we can replace xi and yi in(1.3) with the n-bit words X and Y.
f(X,Y) = XYS3 + XY’S2 + X’YS1 + X’Y’S0 (1.4)
We can now implement the logic unit directly from Equation 1.4, using several n-bit word gates as shown in Figure 1.2. The adder-subtracter can be designed by any of the techniques presented earlier, with appropriate additional connections to X,Y, and S.
Despite its conceptual simplicity, the ALU of figure 1.1 is more expensive and slower than necessary. For n=4, the logic subunit employs about 25 gates and inverters. The multiplexer in Figure 1.2 also requires additional gates.
An n-bit logic unit that realizes all 16 two-variable functions s
The complete 4-bit ALU can therefore more than 100 gates of various kinds and have depth 9 or so. By judicious sharing of functions between the two main subunits, both of these figures can be reduced by a third, as shown in the next topic.