**
Arithmetic-Logic Unit**

** **

** **

The various circuits used to execute data processing instructions are usually combined in a single circuit called an arithmetic-logic unit or ALU. The complexity of an ALU is determined by the way in which its arithmetic instructions are realized. Simple ALUs that performs fixed point addition and subtraction, as well as word based logical operations, can be realized by combinational circuits. ALUs that also perform multiplication and division can be constructed around the circuits developed for these operations in the preceding section. Much more extensive data processing and control logic is necessary to implement floating-point arithmetic in hardware. Some processors having fixed-point ALUs employ special-purpose auxiliary units called arithmetic (co)processors to perform floating-point and other complex numerical functions.

** Combinational ALUs**

The
simplest ALUs combine the functions of twos-complement adder-subtracter with
those of a circuit that generates word-based logic functions of the form ** f(X,Y)**,
for example, AND, XOR, & NOT. They can thus implement most of a CPU’s
fixed-point data-processing instructions. Figure 1.1 outlines an ALU that has
separate subunits for logical and arithmetic operations. The particular case of
operation (logical and arithmetic) to be performed is determined by a “mode”
control line M attached to a two-way multiplexer that channels the required
result to the output bus

Figure 1.1

A basic *n-*bit arithmetic-logic
unit (ALU).

The
specific operation performed by the desired subunit is determined by a select
line ** S** as shown. The ALU’s logical operations are performed
bitwise; that is, the same f is applied to every pair of data lines

The logical
operations in figure can be obtained by generating all four minterms of *f(*** x_{i},y_{i})**, namely,

*m _{3}= *

* *

for
every pair ** x_{i},y_{i} **of data bits and by using the
control lines

** f(x_{i},y_{i}) = m_{3}S_{3} + m_{2}S_{2}
+ m_{1}S_{1} + m_{0}S_{0
}**(1.2)

_{ }

*= **x _{i}y_{i}S_{3} + x_{i}y_{i}’S_{2} + x_{i}’y_{i}S_{1} + x_{i}’y_{i}’S_{0 }*

then we see that every combination of ** S_{3}S_{2}S_{1}S_{0}** produces a different
function. For example, S = 0110 makes

** f(X,Y) = XYS_{3} + XY’S_{2}
+ X’YS_{1} + X’Y’S_{0} ** (1.4)

We can now implement the logic unit directly from Equation 1.4, using several n-bit word gates as shown in Figure 1.2. The adder-subtracter can be designed by any of the techniques presented earlier, with appropriate additional connections to X,Y, and S.

Despite its conceptual simplicity, the ALU of figure 1.1 is more expensive and slower than necessary. For n=4, the logic subunit employs about 25 gates and inverters. The multiplexer in Figure 1.2 also requires additional gates.

Figure 1.2

An *n*-bit logic unit that realizes all 16 two-variable
functions
s

The complete 4-bit ALU can therefore more than 100 gates of various kinds and have depth 9 or so. By judicious sharing of functions between the two main subunits, both of these figures can be reduced by a third, as shown in the next topic.