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ALU Design using Vedic Multiplication Techniques

 The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in the integration of a number of processor cores into one chip. Still the load on the processor is not less in generic system. This load is reduced by supplementing the main processor with Co-Processors, which are designed to work upon specific type of functions like numeric computation, Signal Processing, Graphics etc. The speed of ALU depends greatly on the multiplier. In algorithmic and structural levels, numerous multiplication techniques have been developed to enhance the efficiency of the multiplier which concentrates in reducing the partial products and the methods of their addition but the principle behind multiplication remains the same in all cases. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. Employing these techniques in the computation algorithms of the coprocessor will reduce the complexity, execution time, area, power etc. Though there are many sutras employed to handle different sets of numeric, exploring each one gives new results. Our work has proved the efficiency of Urdhva Triyagbhyam– Vedic method for multiplication which strikes a difference in the actual process of multiplication itself. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps. This sutra is to be used to build a high speed power efficient multiplier in the coprocessor.                                               

The uses of Vedic Mathematics shows its application in fast calculations (multiplication, division, squaring, cubing, square root, cube root), trigonometry, three- dimensional coordinate geometry, solution of plane and spherical triangles, linear and non-linear differential equations, matrices and determinants, log and exponential. The most interesting point is to note that the Vedic Mathematics provides unique solutions in several instances where trial and error method is available at present. Vedic Mathematics offers a fresh and highly efficient approach to mathematics covering a wide range - starts with elementary multiplication and concludes with a relatively advanced topic, the solution of non-linear partial differential equations. But the Vedic scheme is not simply a collection of rapid methods; it is a system, a unified approach. Vedic Mathematics extensively exploits the properties of numbers in every practical application. Using these Vedic techniques various arithmetic modules can be designed and integrated into a Vedic ALU, which is compatible for Co-Processors. This Vedic Co-Processor will be more efficient than the conventional one. 



Designing of high speed floating point multipliers is a great challenge because of its great dynamic range, high precision and easy operating rules. Floating point numbers have wide applications, such as scientific calculations, computer graphics, digital signal processors etc. With the increasing requirements of floating point multiplications for the high-speed data signal processing and the scientific operation, the requirements for the high-speed hardware floating point multipliers have become more and more exigent.

Multiplication is realized by shifts generating partial products that are subsequently added together, which yield the output of the multiplier. The partial products are generated through the Baugh Wooley. Multiplication of two N bit sign digit floating numbers yield N×N partial products. If Conventional two input N bit adders are used, N−1 adders are required to sum the partial products, since each adder reduces the number of partial products by one.


Design Preliminaries


Decimal multiplication performs the computation P = X × Y. Where X is the multiplicand, Y is the multiplier and P is the product. It is assumed that if X and Y both are ‘N’ bits then the values of P must be ‘2N’ bits. A floating point number consists of a mantissa (M) and an exponent (e) as shown in equation (1). The sign of the mantissa may be represented in different way. One way is to use a two's-complement representation, another common approach is to use a sign magnitude representation where a sign bit (S) decides the sign and mantissa holds the magnitude of the number. The sign of the exponent must also be represented. A common approach is to store the exponent in an excess representation, where the exponent is treated as a positive number from which a constant is subtracted to form the final exponent. The IEEE 754 single precision format is 32 bit wide and uses a 23 bit fraction, an eight bit exponent represented using excess 127, and one bit is used as a sign bit. 

X = M 2e  ---------------------- (1)

X = (-1)S.1.M.2e-excess  --------------------------------- (2)