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abstract
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 FLOATING POINT ALU

 USING ANCIENT VEDIC MATHEMATICS

 

 

 

 

 

 

ABSTRACT

 

 

The endeavor of this project is to create a high speed ALU. The main aim is to synthesize an ALU which takes considerably less time than contemporary ALUs using commonly available hardware and implementing age old Vedic Mathematics   algorithms that take lesser time to execute than conventional ones. In this project, each section of the ALU has been thoroughly discussed along with the techniques that have been used here to minimize delays. A comparative analysis has been done to find how well the Vedic ALU performs in comparison with Conventional ALUs using different architecture and inferences have been drawn accordingly. And the conclusion that mathematical shortcuts can help in bringing about faster ALUs discussed as well.

 

High speed ALU using Vedic mathematics and VHDL

 

The 21st century world is full of electronic gadgets. They are present everywhere and are very much indispensible in our life. Also it is a fact that the heart of every gadget is an electronic circuit called ALU. It is the ALU that determines the performance of every gadget on which we so heavily depend. So the performance of ALU is so very crucial to us.

In this project, we have implemented 8-bit floating point ALU using ancient Vedic mathematics, which offered substantial amount of hardware reduction and quantifiably explicit reduction of  propagation delay  compared to existing reported ALUs so far.

 

Why do we need a high speed ALU?

 

As our needs increase, the need for processing of those needs also increases. With newer demands comes the challenge of processing more and more information at ever increasing speed to adhere to the stipulated time frame. As such we need gadgets that work really fast and help us keep in pace with the dynamic environment. And for faster gadgets we need a faster ALU. An ALU that works significantly faster than its predecessors. So we are presenting an ALU that is smarter in processing but faster in execution as well.

 

Roadmap to a high speed ALU

 

The main challenge before us to make our ALU work faster than others was that we had to limit our hardware requirement to what is available in the market now-a- days. So for our ALU to run fast we had to significantly modify the algorithms that contemporary ALUs use so that they take lesser time to execute. and for this we needed smarter algorithms for simple mathematical operations that needed lesser time  this need of ours for smarter mathematical algorithms took us to the doorstep of Ancient  Indian VEDIC MATHEMATICS.

 

Coding of the algorithms of high speed ALU

 

We have written the codes of the algorithm for our ALU in VHDL. The key advantage of VHDL, when used for systems design, is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).

 

Another benefit is that VHDL allows the description of a concurrent system. VHDL is a dataflow language, unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time. This makes VHDL the ideal language of our project.