The 89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The on-chip Flash allows the program memory to be reprogrammed in-system.
• Compatible with MCS-51™ Products
• 4K Bytes of In-System Reprogrammable Flash Memory.
• Fully Static Operation: 0 Hz to 24 MHz
• Three-level Program Memory Lock
• 128 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Two 16-bit Timer/Counters
• Six Interrupt Sources
• Programmable Serial Channel
• Low-power Idle and Power-down Modes
Port 3.0- RXD (serial input port)
Port 3.1- TXD (serial output port)
Port 3.2- INT0 (external interrupt 0)
Port 3.3- INT1 (external interrupt 1)
Port 3.4- T0 (timer 0 external input)
Port 3.5- T1 (timer 1 external input)
Port 3.6- WR (external data memory write strobe)
Port 3.7- RD (external data memory read strobe)
Port 0-Port 0 is an 8-bit open-drain bi-directional I/O port.
Port 1,2&3-Port 1,2&3 are an 8-bit bi-directional I/O port with internal pull-ups.
ALE/PROG-Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory.
PSEN-Program Store Enable is the read strobe to external program memory.
EA/VPP-External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.
XTAL1-Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2-Output from the inverting oscillator amplifier.
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.
In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers and data for the entire array or until the end of the object file is reached.
Status of External Pins During Idle and Power-down Modes