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74LS74 D type flip/flop

This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated.


Pin Arrangement


Function Table


H = HIGH Logic Level

X = Either LOW or HIGH Logic Level

L = LOW Logic Level

UP Arrow= Positive-going Transition

Q0 = The output logic level of Q before the indicated input conditions were