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Simulation Results Analysis:**

Synthesis results have been carried out using XILINX-8.2i simulator and simulation results have been carried out using Modelsim simulator. The snapshot which has been shown in Fig. 8, are describing the design summary of the square root processor. The same figure also describes that the utilization table like number of slices, number of 4 inputs LUTs and number of IOBs required. The whole Square Root architecture has been described in Fig. 9. And Fig. 10, Fig.-11, Fig.-12 describes the inside architecture of Square Root processor pert by part from 1 to 3. Internal architecture blocks of each processing units of main Square Root processor is described in Fig. 13. Farther internal architecture has been described in Fig. 14.

Fig. 8: Design summary

Fig. 9: Main Square Root Architecture

Fig. 10: Square Root Processor Part-1

Fig. 11: Square Root Processor Part-2

Fig. 12: Square Root Processor Part-3

Fig. 13: Internal Architecture of Each Processor part-1

Fig. 14: Farther Internal Architecture of Each Processor part-2

Simulation results have been compared with other traditional square root extraction methodologies. The plot shown in fig. 15 describes the number of slice available and utilized, as well as the % of utilization. In the plot first one represents Goldsmidt algorithm, second one Newton-Raphson method, third one Min-Max, and the last one was our proposed method. Number of I/P LUTs (Look Up Tables) available & utilized, and number of Bonded I/O Bs (Input-Output Buffers) available & utilized has been shown in Fig. 16 and Fig. 17.

Fig. 15: No of slices available & utilized

Fig.-16: No of I/P LUT available & utilized

Fig.-17: No of Bonded I/O Bs