Divider using Dhvajanka Sutra:
Mathematical Modeling of division operation (“On top of the flag”)
Consider the number to be divided by assuming that both the numbers are of same length (here the length is (n/2)-1) and x is the radix. To execute the division operation easily and efficiently by ‘Dhvajanka’ sutra (“On top of the flag”) methodology described in the ancient Indian Vedic Mathematics, Dividend must have greater length than Divisor. Consider again a number A’ which can be represented as
can be mapped with where the condition of mapping is . The quotient Q can be determined as
(16) The term ,where x is the radix is to be extracted by Exponent Extraction Unit(EEU). In Binary number system, the radix ‘x’ is equal to 2. Then from equation (10) it is obvious that the result of is needed to be shifted right by n/2 terms which has been shown in Fig.-5, to get the actual quotient. The mathematical modeling of division operation by “Vertically and Crosswise” methodology has been described in the following subsection.
Fig. 5: RTL representation of Exponent Extraction Unit
The architecture shown in Fig.-5 consists of some elementary building blocks like left shifter, right shifter, incrementer and demultiplexer. Incrementer calculates the exponent of the number which is controlled by the shifted bit. The clock applied to the shifter is also controlled by the shifted bit. If the shifted bit is ‘1’ then the shifters stops further shifting. Fig.-6 shows the architectural description of division operation using “On top of the flag” Sutra. The Dividend of N bits is divided into two equal N/2 bits. The most significant part is fed to the subtractor which is of N/2+1 bits size. Single bit zero padding is done in subtractor module to the left. The division procedure incorporated here is non-restoring type of division. The carry output after the subtraction is fed to the quotient array register as quotient.
The quotient array register stores the quotients based on the iterated value which is used as position signal. The value N/2+1 is stored in the decrementer initially to count and check the specified iteration. After each iteration, both the left shifters are updated by shifting until the decremented value reaches zero.
The Divider architecture combining the exponent extraction and the ‘Dhvajanka’ Sutra is shown in Fig.-8. The basic building blocks of the architecture are (i) Exponent Extraction Unit, (ii) Divider using ‘Dhvajanka’ sutra, (iii) Subtractor, (iv) Quotient Array Register and (v) Bidirectional Shift Register. Zero padding is needed to represent a number to higher number of bits. For example if a four bit number “0111” is represented in eight bit format then the representation becomes “00000111”. Here zero padding has been executed based on the requirement. Bidirectional shift register performs the operation of shifting both to the left or right depending upon the control signal ‘carry’ from the second subtractor. If carry=0 then the input bits are shifted to the left and if carry=1 then input bits are shifted to the right. The result of the second subtractor is fed to the shifter to control number shifting. The contents of the Quotient Array Register are the input to the Bidirectional Shift register.
Fig. 6: Divider architecture using Dhvajanka Sutra