In this project we report on a square root architecture design based on ancient Vedic methodology and has been simulated in Xilinx-8.2i simulator. For designing the square root processor, intermediate arithmetical function has been implemented using the same ancient Vedic methodologies, which offered a carry free implementation for all the cases. The reported architecture offered the several features like minimization of propagation delay and also minimization of power consumption compared with the other design methodologies like N-R, Goldsmidth, and M-M architectures reported so-far. The approach used in this work further reduced area requirements by incorporating a small multiplier to generate some of the constants rather than using additional look-up tables. The resulting arithmetic unit also exhibits high throughput and moderate latency as compared with other FPU implementations of leading architectures. Further work is going on progress regarding the layout of the square root processor architecture design.