Modulus subtractor shown in Fig.-7 consists of two cascaded parallel adders. The XOR gate connected to the first stage adder is to complement one of the two inputs. The first stage adder plays an important role in executing two’s complement addition operation. The active low value of the carry out signal of the first stage addition indicates negative result taken from the first stage adder output in two’s complemented form which is again converted to achieve the modulus value by the second stage adder. In second stage adder, the first stage result is complemented by two’s complement method depending upon the carry out signal of the first stage.
Fig. 7: Architecture of 8 bit Modulus Subtractor