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ABSTRACT

       Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique of calculations based on 16 Sutras (Formulae). The idea for designing the square root processor a number was adopted from ancient Indian mathematics “Vedas”. On account of the Vedic formulas, the square root of any number is generated in one step which reduces the iteration. A prototype of 16 bit square root processor has been implemented and their functionality has been experimented on a Virtex-2 FPGA board. The IEEE-754 single floating point implementation of that methodologies and their application to the square root implementation ensure quantifiably explicit reduction of hardware utilization in comparison with earlier reported architectures like digit by digit algorithm, Newton-Raphson and polynomial approximation method which are most commonly used architectures. The functionality of these circuits was checked and performance parameters such as utilization of the Processing Elements (PEs), Flip-Flops (FFs), digital gates were calculated through VHDL on a Xilinx- 8.2i Simulator. The  resulting square root of 16 bit number consumes only ~512 logic elements  with ~750 FFs. Almost 75% improvement in terms of hardware utilization has been achieved from  earlier reported square root implementation, e.g. Newton-Raphson method, Polynomial Approximation method and digit by digit implementation.