INTRODUCTION of VEDIC divider
Division is a very important arithmetic function of mathematical world. It is very frequently used in computational mathematics. Today’s processors perform division tasks based on traditional methods. This methods are The Restoring method, Non-Restoring method, SRT division etc. In the above described methods all are suffering from a common problem that is a repeated carry propagation from one step of the algorithm to the other. The numbers of iteration steps are also more. That’s why, the overall propagation delay is high resulting in a high value of EDP.
Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique of calculations based on 16 Sutras (Formulae). The idea for designing the square root processor a number was adopted from ancient Indian mathematics “Vedas”. On account of the Vedic formulas, the carry proapagtion problem is greatly mitigated which reduces the overall propagation delay. The number of iteration is also decreased as compared to the traditional algorithms in place today. That’s why if we implement this Division method in FPGA chip then the processing will be faster than the other traditional methods.